• ISSN 1908-3238 (Online)

IMPLEMENTATION AND MODELING OF LOW POWER SLEEPY STACK SRAM

Authors: Rahul Kakkar, Sumeet Goyal, Joginder Singh, Dishant Khosla, Sohni Singh
20-Aug-2022 191 Views DOWNLOAD

For the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However, sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 μW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 μW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

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